The Reduceron
Matthew Naylor, University of York
Date and time: Friday 24th April 2009 at 14:00
Location: UG40, School of Computer Science
Host: Dan
Efficient evaluation of high-level functional programs on conventional computers is a big challenge. Sophisticated implementation techniques are needed to exploit architectural features designed for low-level imperative execution. What's more, conventional computers have inherent limitations when it comes to running functional programs.
In this talk, I will explore what is possible when some of these constraints and limitations are lifted. I will do so with reference to the Reduceron, a special-purpose reduction machine for lazy functional languages, prototyped on an FPGA. I will focus on some architectural features that allow for an efficient yet simple implementation.