Balsa Verification Examples Page

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Case studies

• CSP delay-insensitivity verification of the False Variable circuit redesign using FDR (see script).
• CSP deadlock checking of the Instruction fetching phase of a simplified Balsa asynchronous processor using FDR (see script).
• CSP verification of a distributed coloring algorithm using FDR (see script).
• CSP verification of a (balanced) tree arbiter using FDR (see script).
• CSP verification of Yakovlev’s control circuit for counterflow pipeline (see script)