Energy efficient hardware acceleration of multimedia processing tools

Created by W.Langdon from gp-bibliography.bib Revision:1.3872

@PhdThesis{Andrew_Kinane,
  author =       "Andrew Kinane",
  title =        "Energy efficient hardware acceleration of multimedia
                 processing tools",
  school =       "School of Electronic Engineering, Dublin City
                 University",
  year =         "2006",
  address =      "Ireland",
  month =        may,
  keywords =     "genetic algorithms, genetic programming",
  URL =          "http://doras.dcu.ie/17985/",
  URL =          "http://doras.dcu.ie/17985/1/Andrew_Kinane.pdf",
  URL =          "http://www.eeng.dcu.ie/~kinanea/thesis/abstract.txt",
  URL =          "http://www.eeng.dcu.ie/~kinanea/thesis/kinane_final.pdf",
  size =         "263 pages",
  abstract =     "The world of mobile devices is experiencing an ongoing
                 trend of feature enhancement and general-purpose
                 multimedia platform convergence. This trend poses many
                 grand challenges, the most pressing being their limited
                 battery life as a consequence of delivering
                 computationally demanding features. The envisaged
                 mobile application features can be considered to be
                 accelerated by a set of underpinning hardware blocks.
                 Based on the survey that this thesis presents on modern
                 video compression standards and their associated
                 enabling technologies, it is concluded that tight
                 energy and throughput constraints can still be
                 effectively tackled at algorithmic level in order to
                 design re-usable optimised hardware acceleration
                 cores.

                 To prove these conclusions, the work in this thesis is
                 focused on two of the basic enabling technologies that
                 support mobile video applications, namely the Shape
                 Adaptive Discrete Cosine Transform (SA-DCT) and its
                 inverse, the SA-IDCT. The hardware architectures
                 presented in this work have been designed with energy
                 efficiency in mind. This goal is achieved by employing
                 high level techniques such as redundant computation
                 elimination, parallelism and low switching computation
                 structures. Both architectures compare favourably
                 against the relevant prior art in the literature.

                 The SA-DCT/IDCT technologies are instances of a more
                 general computation -- namely, both are Constant Matrix
                 Multiplication (CMM) operations. Thus, this thesis also
                 proposes an algorithm for the efficient hardware design
                 of any general CMM-based enabling technology. The
                 proposed algorithm leverages the effective solution
                 search capability of genetic programming. A bonus
                 feature of the proposed modelling approach is that it
                 is further amenable to hardware acceleration. Another
                 bonus feature is an early exit mechanism that achieves
                 large search space reductions. Results show an
                 improvement on state of the art algorithms with future
                 potential for even greater savings.",
  notes =        "Supervisor: Dr. Noel E. O'Connor.

                 ID Code: 17985",
}

Genetic Programming entries for Andrew Kinane

Citations