Algorithms for Topology Synthesis of Analog Circuits

Created by W.Langdon from gp-bibliography.bib Revision:1.3973

@PhdThesis{Angan:Das:thesis,
  author =       "Angan Das",
  title =        "Algorithms for Topology Synthesis of Analog Circuits",
  school =       "Electrical Engineering, University of Cincinnati",
  year =         "2008",
  address =      "USA",
  month =        "7 " # nov,
  keywords =     "genetic algorithms, genetic programming, EHW,
                 automated analogue design, topology generation,
                 optimization, evolutionary algorithms, filter design,
                 graph grammar",
  URL =          "https://etd.ohiolink.edu/!etd.send_file?accession=ucin1227204301.pdf",
  URL =          "http://rave.ohiolink.edu/etdc/view?acc_num=ucin1227204301",
  size =         "180 pages",
  abstract =     "In today's world, with ever increasing design
                 complexity and constantly shrinking device sizes, the
                 microelectronics industry faces the need to develop an
                 entire system on a single chip (SoC). This need gives
                 rise to the responsibility of developing mature
                 Computer-Aided-Design (CAD) tools to tackle such
                 complexities. Unlike digital CAD tools, automated
                 synthesis tools for the irreplaceable analogue sections
                 are still immature. Circuit-level analog synthesis
                 comprises of two steps — Topology formation and
                 Sizing of the topology. Topology selection and topology
                 generation are two approaches to topology formation.
                 Research in topology selection has almost been
                 discontinued owing to heavy designer dependency. But
                 with the advent of evolutionary techniques like Genetic
                 Algorithm (GA) and Genetic Programming (GP), topology
                 generation gained popularity. Topology generation is
                 the art of generating device level circuit schematics
                 satisfying user specifications. This thesis makes a
                 genuine endeavour to develop topology generation tools
                 individually for both passive analogue circuits
                 involving R, L, and C components and active circuits
                 that involve additional MOS devices.

                 For passive circuits, we present a GA-based synthesis
                 framework, where the component values for the first set
                 of circuits are set through a deterministic
                 computational technique. Further, the crossover
                 technique for breeding off-springs from parent
                 solutions obeys certain constraints to ensure the
                 formation of structurally correct circuits. The work
                 has been further extended with the introduction of
                 novel selection and crossover strategies. The above
                 techniques have been successful in synthesizing various
                 low-pass and high-pass filter designs.

                 In the pursuit of developing an active circuit topology
                 generator, we have developed a self-learning
                 optimization algorithm involving multiple design
                 variables. To measure the effectiveness of this
                 technique, we applied it first to a relatively easier
                 domain viz. MPLS computer network topology design. The
                 tool produced optimal solutions for most of the test
                 cases considered.

                 Drawing inspiration from the above work, we have
                 extended the technique to active analogue circuit
                 synthesis. Here, we use a building block library that
                 is adaptively formed based on the self-learning
                 approach. It starts with basic elements like PMOS and
                 NMOS and gradually includes bigger and functionally
                 more meaningful blocks as the synthesis run progresses.
                 Our next work on active synthesis incorporates the
                 advantages of both a conventional GA as well as an
                 augmented version of the dynamically formed building
                 block library. Using the above techniques, we have
                 synthesized two opamp and ring oscillator
                 designs.

                 Finally, to strengthen the analogue circuit topology
                 design approach and increase its universal appeal
                 further, we have developed a graph grammar based
                 framework. Appropriate production rules are used to
                 generate circuits through derivation trees. Our
                 approach has certain advantages when compared to other
                 tree-based techniques like GP. The framework also
                 incorporates the concept of dynamic extraction and
                 subsequent use of better building blocks. The work has
                 been extended further to replace the numerical
                 techniques used in quantifying the suitability of a
                 block, with a fuzzy logic based inference system. The
                 developed tool has been successful in synthesizing
                 opamp and vco designs, producing both manual-like
                 designs as well as novel designs.",
  notes =        "Table 7.1 says not GP

                 ucin1227204301

                 Supervisor Ranga Vemur",
}

Genetic Programming entries for Angan Das

Citations