Intrinsic evolvable hardware for combinatorial synthesis based on SoC+FPGA and GPU platforms

Created by W.Langdon from gp-bibliography.bib Revision:1.3872

  author =       "Carlos Ivan {Camargo Bareno} and 
                 Cesar Augusto {Pedraza Bonilla} and Luis Fernado Nino and 
                 Jose Ignacio {Martinez Torre}",
  title =        "Intrinsic evolvable hardware for combinatorial
                 synthesis based on SoC+FPGA and GPU platforms",
  booktitle =    "GECCO '11: Proceedings of the 13th annual conference
                 companion on Genetic and evolutionary computation",
  year =         "2011",
  editor =       "Natalio Krasnogor and Pier Luca Lanzi and 
                 Andries Engelbrecht and David Pelta and Carlos Gershenson and 
                 Giovanni Squillero and Alex Freitas and 
                 Marylyn Ritchie and Mike Preuss and Christian Gagne and 
                 Yew Soon Ong and Guenther Raidl and Marcus Gallager and 
                 Jose Lozano and Carlos Coello-Coello and Dario Landa Silva and 
                 Nikolaus Hansen and Silja Meyer-Nieberg and 
                 Jim Smith and Gus Eiben and Ester Bernado-Mansilla and 
                 Will Browne and Lee Spector and Tina Yu and Jeff Clune and 
                 Greg Hornby and Man-Leung Wong and Pierre Collet and 
                 Steve Gustafson and Jean-Paul Watson and 
                 Moshe Sipper and Simon Poulding and Gabriela Ochoa and 
                 Marc Schoenauer and Carsten Witt and Anne Auger",
  isbn13 =       "978-1-4503-0690-4",
  keywords =     "genetic algorithms, genetic programming, GPU: Poster",
  pages =        "189--190",
  month =        "12-16 " # jul,
  organisation = "SIGEVO",
  address =      "Dublin, Ireland",
  DOI =          "doi:10.1145/2001858.2001964",
  publisher =    "ACM",
  publisher_address = "New York, NY, USA",
  abstract =     "This paper presents a novel a parallel genetic
                 programming (PGP) Boolean synthesis implementation on a
                 low cost cluster of an embedded open platform called
                 SIE. Some tasks of the PGP have been accelerated
                 through a hardware coprocessor called FCU, that allows
                 to evaluate individuals onchip as intrinsic evolution.
                 Results have been compared with GPU and HPC
                 implementations, resulting in speedup values up to
                 approximately 2 and 180 respectively.",
  notes =        "Also known as \cite{2001964} Distributed on CD-ROM at

                 ACM Order Number 910112.",

Genetic Programming entries for Carlos Ivan Camargo Bareno Cesar Pedraza Bonilla Luis Fernando Nino Vasquez Jose Ignacio Martinez Torre