Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished

Created by W.Langdon from gp-bibliography.bib Revision:1.4067

@InProceedings{Ceska:2017:ICCAD,
  author =       "Milan Ceska and Jiri Matyas and Vojtech Mrazek and 
                 Lukas Sekanina and Zdenek Vasicek and Tomas Vojnar",
  title =        "Approximating Complex Arithmetic Circuits with Formal
                 Error Guarantees: 32-bit Multipliers Accomplished",
  booktitle =    "Proceedings of 36th IEEE/ACM International Conference
                 On Computer Aided Design (ICCAD)",
  year =         "2017",
  editor =       "Iris Bahar and Sri Parameswaran",
  pages =        "416--423",
  address =      "Irvine, CA, USA",
  month =        nov # " 13-16",
  publisher =    "Institute of Electrical and Electronics Engineers",
  keywords =     "genetic algorithms, genetic programming, Cartesian
                 Genetic Programming, approximate computing, logical
                 synthesis,",
  isbn13 =       "978-1-5386-3093-8",
  language =     "english",
  URL =          "http://www.fit.vutbr.cz/research/view_pub.php?id=11420",
  DOI =          "doi:10.1109/ICCAD.2017.8203807",
  size =         "8 pages",
  abstract =     "We present a novel method allowing one to approximate
                 complex arithmetic circuits with formal guarantees on
                 the approximation error. The method integrates in a
                 unique way formal techniques for approximate
                 equivalence checking into a search-based circuit
                 optimisation algorithm. The key idea of our approach is
                 to employ a novel search strategy that drives the
                 search towards promptly verifiable approximate
                 circuits. The method was implemented within the ABC
                 tool and extensively evaluated on functional
                 approximation of multipliers (with up to 32-bit
                 operands) and adders (with up to 128-bit operands).
                 Within a few hours, we constructed a high-quality
                 Pareto set of 32-bit multipliers providing trade-offs
                 between the circuit error and size. This is for the
                 first time when such complex approximate circuits with
                 formal error guarantees have been derived, which
                 demonstrates an outstanding performance and scalability
                 of our approach compared with existing methods that
                 have either been applied to the approximation of
                 multipliers limited to 8-bit operands or statistical
                 testing has been used only. Our approach thus
                 significantly improves capabilities of the existing
                 methods and paves a way towards an automated design
                 process of provably correct circuit approximations.",
  notes =        "https://iccad.com/2017_accepted_papers",
}

Genetic Programming entries for Milan Ceska Jiri Matyas Vojtech Mrazek Lukas Sekanina Zdenek Vasicek Tomas Vojnar

Citations