Evolving Static Hardware Redundancy for Defect Tolerant FPGAs
Created by W.Langdon from
gp-bibliography.bib Revision:1.2031
@PhdThesis{Djupdal:thesis,
author = "Asbjoern Djupdal",
title = "Evolving Static Hardware Redundancy for Defect
Tolerant {FPGAs}",
school = "Department of Computer and Information Science,
Faculty of Information Technology, Mathematics and
Electrical Engineering, Norwegian University of Science
and Technology",
year = "2008",
address = "Trondheim",
month = "24 " # apr,
isbn13 = "978-82-471-6874-5",
keywords = "genetic algorithms, genetic programming, cartesian
genetic programming, EHW",
URL = "
http://www.idi.ntnu.no/research/doctor_theses/djupdal.pdf",
size = "136 pages",
abstract = "Integrated circuits have been in constant progression
since the first prototype in 1958. The semiconductor
industry has maintained a constant rate of
miniaturisation of transistors and wires, resulting in
ever increasing speed, size and complexity of circuits.
One challenge that has always been present is reduced
yield due to production defects. A certain amount of
chips must be scrapped because production defects have
rendered the chips unusable. Recent predictions suggest
that the average number of production defects per chip
will rise drastically in the future as CMOS scaling
approaches the physical limits of what is possible to
manufacture. If these predictions are true, circuits
should exhibit some level of tolerance to defects so to
keep yield at acceptable levels.
The main contribution of the thesis is to the field of
defect tolerance, with a focus on FPGAs. Apart from the
widespread employment of FPGAs, two technical reasons
make the FPGA especially suited for inclusion of defect
tolerance techniques. The regular structure of the FPGA
can be exploited for efficient redundancy techniques.
In addition, the FPGA can be seen as a bridge between
production and the application designer. Through defect
tolerance techniques incorporated transparently in the
FPGA, a fully functioning gate array can be provided to
the application designer despite defects from
production.
The approach taken in this thesis is to search for new
ways of introducing static hardware redundancy in a
circuit through the application of artificial
evolution. However, the challenge of applying
evolutionary techniques provided a secondary
contribution. The work provides a contribution to the
field of artificial evolution and the subfield
evolvable hardware (EHW) by addressing ways in which
such techniques may be applied to search for
non-specifiable structures. The work is also bridging
the fields of EHW and traditional hardware design and
reliability metrics have been investigated for the
purpose of comparing evolved and traditionally designed
circuits.
Redundant structures are first evolved for gate level
circuits where both voter based solutions and more
intricate non-voter based solutions are achieved.
Transistor level redundancy structures are targeted
next to approach the main goal of defect tolerance for
FPGAs. A defect tolerant inverter is evolved which
forms the basis of a general defect tolerance
technique, termed the Multiple Short-Open (MSO)
technique. The FPGA look-up table (LUT) is one of the
essential components of the FPGA and a defect tolerant
LUT is, therefore, constructed applying the MSO
technique. An evolutionary experiment is also conducted
where a defect tolerant 1-input LUT is evolved
directly.",
notes = "http://www.idi.ntnu.no/news/index.php?news=112
24th of April Asbjoern Djupdal completed his trial
lecture and thesis defence, and he will eventually be
awarded the PhD degree. The PhD was completed at the
Computer Architecture and Design group, with associate
professor Pauline Haddow as supervisor.
He defended his PhD thesis: Evolving Static Hardware
Redunancy for Defect Tolerant FPGAs",
}
Genetic Programming entries for
Asbjoern Djupdal