Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Created by W.Langdon from gp-bibliography.bib Revision:1.4524

  author =       "Roland Dobai and Lukas Sekanina",
  title =        "Low-Level Flexible Architecture with Hybrid
                 Reconfiguration for Evolvable Hardware",
  journal =      "ACM Transactions on Reconfigurable Technology and
  year =         "2015",
  volume =       "8",
  number =       "3",
  pages =        "20:1--20:24",
  month =        may,
  keywords =     "genetic algorithms, genetic programming, cartesian
                 genetic programming, EHW, Architecture, Zynq, circuit
                 design, evolvable hardware, image filter,
  publisher =    "ACM",
  acmid =        "2700414",
  ISSN =         "1936-7406",
  URL =          "http://www.fit.vutbr.cz/~sekanina/pubs.php.en?id=10394",
  DOI =          "doi:10.1145/2700414",
  size =         "24 pages",
  abstract =     "Field-programmable gate arrays (FPGAs) can be
                 considered to be the most popular and successful
                 platform for evolvable hardware. They allow one to
                 establish and later reconfigure candidate solutions.
                 Recent work in the field of evolvable hardware includes
                 the use of virtual and native reconfigurations. Virtual
                 reconfiguration is based on the change of functionality
                 by hardware components implemented on top of FPGA
                 resources. Native reconfiguration changes the FPGA
                 resources directly by means provided by the FPGA
                 manufacturer. Both of these approaches have their
                 disadvantages. The virtual reconfiguration is
                 characterized by lower maximal operational frequency of
                 the resulting solutions, and the native reconfiguration
                 is slower. In this work, a hybrid approach is used
                 merging the advantages while limiting the disadvantages
                 of the virtual and native reconfigurations. The main
                 contribution is the new low-level architecture for
                 evolvable hardware in the new Zynq-7000
                 all-programmable system-on-chip. The proposed
                 architecture offers high flexibility in comparison with
                 other evolvable hardware systems by considering direct
                 modification of the reconfigurable resources. The
                 impact of the higher reconfiguration time of the native
                 approach is limited by the dense placement of the
                 proposed reconfigurable processing elements. These
                 processing elements also ensure fast evaluation of
                 candidate solutions. The proposed architecture is
                 evaluated by evolutionary design of switching image
                 filters and edge detectors. The experimental results
                 demonstrate advantages over the previous approaches
                 considering the time required for evolution, area
                 overhead, and flexibility.",

Genetic Programming entries for Roland Dobai Lukas Sekanina