Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming

Created by W.Langdon from gp-bibliography.bib Revision:1.4524

  author =       "Zbysek Gajda and Lukas Sekanina",
  title =        "Gate-Level Optimization of Polymorphic Circuits Using
                 Cartesian Genetic Programming",
  booktitle =    "2009 IEEE Congress on Evolutionary Computation",
  year =         "2009",
  editor =       "Andy Tyrrell",
  pages =        "1599--1604",
  address =      "Trondheim, Norway",
  month =        "18-21 " # may,
  organization = "IEEE Computational Intelligence Society",
  publisher =    "IEEE Press",
  isbn13 =       "978-1-4244-2959-2",
  file =         "P186.pdf",
  DOI =          "doi:10.1109/CEC.2009.4983133",
  abstract =     "Polymorphic digital circuits contain ordinary and
                 polymorphic gates. In the past, Cartesian Genetic
                 Programming (CGP) has been applied to synthesize
                 polymorphic circuits at the gate level. However, this
                 approach is not scalable. Experimental results
                 presented in this paper indicate that larger and more
                 efficient polymorphic circuits can be designed by a
                 combination of conventional design methods (such as
                 BDD, Espresso or ABC System) and evolutionary
                 optimization (conducted by CGP). Proposed methods are
                 evaluated on two benchmark circuits - Multiplier/Sorter
                 and Parity/Majority circuits of variable input size.",
  keywords =     "genetic algorithms, genetic programming, cartesian
                 genetic programming",
  notes =        "CEC 2009 - A joint meeting of the IEEE, the EPS and
                 the IET. IEEE Catalog Number: CFP09ICE-CDR",

Genetic Programming entries for Zbysek Gajda Lukas Sekanina