Importance sampled circuit learning ensembles for robust analog IC design

Created by W.Langdon from gp-bibliography.bib Revision:1.4504

  author =       "Peng Gao and Trent McConaghy and Georges Gielen",
  title =        "Importance sampled circuit learning ensembles for
                 robust analog IC design",
  booktitle =    "IEEE/ACM International Conference on Computer-Aided
                 Design, ICCAD 2008",
  year =         "2008",
  pages =        "396--399",
  address =      "San Jose, CA, USA",
  month =        "10-13 " # nov,
  keywords =     "genetic algorithms, genetic programming, EHW, analogue
                 integrated circuits, analogue-digital conversion,
                 importance sampling, integrated circuit design,
                 waveform generators, ISCLEs-specific library, Moore's
                 Law, analog IC design, block topology, boosting
                 algorithm, digital-sized circuits, flash A-D converter,
                 importance sampling, learning ensembles, multi-topology
                 sizing technique, sinusoidal function generator, Analog
                 integrated circuits, Assembly, Boosting, Circuit
                 topology, Design methodology, Monte Carlo methods,
                 Moore's Law, Robustness, Signal generators, Software
  isbn13 =       "978-1-4244-2819-9",
  URL =          "",
  DOI =          "doi:10.1109/ICCAD.2008.4681604",
  size =         "4 pages",
  abstract =     "This paper presents ISCLEs, a novel and robust analog
                 design method that promises to scale with Moore's Law,
                 by doing boosting-style importance sampling on
                 digital-sized circuits to achieve the target analog
                 behaviour. ISCLEs consists of: (1) a boosting algorithm
                 developed specifically for circuit assembly; (2) an
                 ISCLEs-specific library of possible digital-sized
                 circuit blocks; and (3) a recently-developed
                 multi-topology sizing technique to automatically
                 determine each block's topology and device sizes.
                 ISCLEs is demonstrated on design of a sinusoidal
                 function generator and a flash A/D converter, showing
                 promise to robustly scale with shrinking process
  notes =        "also known as \cite{4681604}",

Genetic Programming entries for Peng Gao Trent McConaghy Georges G E Gielen