Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure

Created by W.Langdon from gp-bibliography.bib Revision:1.3872

@Article{Kim:2009:GPEM,
  author =       "Kyung-Joong Kim and Adrian Wong and Hod Lipson",
  title =        "Automated synthesis of resilient and tamper-evident
                 analog circuits without a single point of failure",
  journal =      "Genetic Programming and Evolvable Machines",
  year =         "2010",
  volume =       "11",
  number =       "1",
  pages =        "35--59",
  month =        mar,
  keywords =     "genetic algorithms, genetic programming, evolvable
                 hardware, Analog circuit, Robustness, Evolutionary
                 strategies, Low-pass filter, Hardware implementation,
                 Tamper-evident circuits, coevolution",
  ISSN =         "1389-2576",
  URL =          "http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.654.7781",
  DOI =          "doi:10.1007/s10710-009-9085-2",
  abstract =     "This study focuses on the use of genetic programming
                 to automate the design of robust analog circuits. We
                 define two complementary types of failure modes:
                 partial short-circuit and partial disconnect, and
                 demonstrated novel circuits that are resilient across a
                 spectrum of fault levels. In particular, we focus on
                 designs that are uniformly robust, and unlike designs
                 based on redundancy, do not have any single point of
                 failure. We also explore the complementary problem of
                 designing tamper-proof circuits that are highly
                 sensitive to any change or variation in their operating
                 conditions. We find that the number of components
                 remains similar both for robust and standard circuits,
                 suggesting that the robustness does not necessarily
                 come at significant increased circuit complexity. A
                 number of fitness criteria, including surrogate models
                 and co-evolution were used to accelerate the
                 evolutionary process. A variety of circuit types were
                 tested, and the practicality of the generated solutions
                 was verified by physically constructing the circuits
                 and testing their physical robustness.",
  notes =        "sec 4.5 {"}We tested the validity of the evolved
                 circuits by building them in reality.{"}. sec 5 {"}no
                 single point of failure. Surprisingly, this robustness
                 did not come at a significant increase in circuit
                 complexity...{"}",
}

Genetic Programming entries for Kyung-Joong Kim Adrian Wong Hod Lipson

Citations