Task Decomposition and Evolvability in Intrinsic Evolvable Hardware

Created by W.Langdon from gp-bibliography.bib Revision:1.4549

  author =       "Tuze Kuyucu and Martin A. Trefzer and 
                 Julian F. Miller and Andy M. Tyrrell",
  title =        "Task Decomposition and Evolvability in Intrinsic
                 Evolvable Hardware",
  booktitle =    "2009 IEEE Congress on Evolutionary Computation",
  year =         "2009",
  editor =       "Andy Tyrrell",
  pages =        "2281--2287",
  address =      "Trondheim, Norway",
  month =        "18-21 " # may,
  organization = "IEEE Computational Intelligence Society",
  publisher =    "IEEE Press",
  isbn13 =       "978-1-4244-2959-2",
  file =         "P631.pdf",
  DOI =          "doi:10.1109/CEC.2009.4983224",
  abstract =     "Many researchers have encountered the problem that the
                 evolution of electronic circuits becomes exponentially
                 more difficult when problems with an increasing number
                 of outputs are tackled. Although this is an issue in
                 both intrinsic and extrinsic evolution experiments,
                 overcoming this problem is particularly challenging in
                 the case of evolvable hardware, where logic and routing
                 resources are constrained according to the given
                 architecture. Consequently, the success of experiments
                 also depends on how the inputs and outputs are
                 interfaced to the evolvable hardware. Various
                 approaches have been made to solve the multiple output
                 problem: partitioning the task with respect to the
                 input or output space, incremental evolution of
                 sub-tasks or resource allocation. However, in most
                 cases, the proposed methods can only be applied in the
                 case of extrinsic evolution. In this paper, we have
                 accordingly, focused on scaling problem of increasing
                 numbers of outputs when logic circuits are
                 intrinsically evolved. We raise a number of questions:
                 how big is the performance drop when increasing the
                 number of outputs? Can the resources of evolvable
                 hardware be structured in a suitable way to overcome
                 the complexity imposed by multiple outputs, without
                 including knowledge about the problem domain? Can
                 available resources in hardware still be efficiently
                 used when pre-structured? In order to answer these
                 questions, different structural implementations are
                 investigated. We have looked at these issues in solving
                 three problems: 4-bit parity, 2-bit adder and 2-bit
  keywords =     "genetic algorithms, genetic programming, cartesian
                 genetic programming",
  notes =        "CEC 2009 - A joint meeting of the IEEE, the EPS and
                 the IET. IEEE Catalog Number: CFP09ICE-CDR",

Genetic Programming entries for Tuze Kuyucu Martin A Trefzer Julian F Miller Andrew M Tyrrell