Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

Created by W.Langdon from gp-bibliography.bib Revision:1.3872

@InProceedings{Mora:2015:ReCoSoC,
  author =       "Javier Mora and Andres Otero and 
                 Eduardo {de la Torre} and Teresa Riesgo",
  booktitle =    "10th International Symposium on Reconfigurable
                 Communication-centric Systems-on-Chip (ReCoSoC)",
  title =        "Fast and compact evolvable systolic arrays on
                 dynamically reconfigurable FPGAs",
  year =         "2015",
  month =        jun,
  keywords =     "genetic algorithms, genetic programming, EHW",
  DOI =          "doi:10.1109/ReCoSoC.2015.7238087",
  abstract =     "Evolvable hardware may be considered as the result of
                 a design methodology that employs an evolutionary
                 algorithm to find an optimal solution to a given
                 problem in the form of a digital circuit. Evolutionary
                 algorithms typically require testing thousands of
                 candidate solutions, taking long time to complete. It
                 would be desirable to reduce this time to a few seconds
                 for applications that require a fast adaptation to a
                 problem. Also, it is important to consider
                 architectures that may operate at high clock speeds in
                 order to reach very speed-demanding situations. This
                 paper presents an implementation on an FPGA of an
                 evolvable hardware image filter based on a systolic
                 array architecture that uses dynamic partial
                 reconfiguration in order to change between different
                 candidate solutions. The neighbour to neighbour
                 connections of the array offer improved performance
                 versus other approaches, like Cartesian Genetic
                 Programming derived circuits. Time savings due to
                 faster evaluation compensate the slower reconfiguration
                 time compared with virtual reconfiguration approaches,
                 but, at any rate, reconfiguration time has been
                 improved also by reducing the elements to reconfigure
                 to just the LUT contents of the configurable blocks.
                 The techniques presented in this paper lead to circuits
                 that may operate at up to 500 MHz (in a Virtex-5),
                 filtering 500 megapixels per second, the processing
                 element size of the array is reduced to 2 CLBs, and
                 over 80000 evaluations per second in a multiple array
                 structure in an FPGA permit to obtain good quality
                 filters in around 3 seconds of evolution time.",
  notes =        "Centro de Electron. Ind., Univ. Politec. de Madrid,
                 Madrid, Spain

                 Also known as \cite{7238087}",
}

Genetic Programming entries for Javier Mora Andres Otero Eduardo de la Torre Teresa Riesgo

Citations