Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation

Created by W.Langdon from gp-bibliography.bib Revision:1.3872

@InProceedings{Mrazek:2015:EuroGP,
  author =       "Vojtech Mrazek and Zdenek Vasicek",
  title =        "Evolutionary Design of Transistor Level Digital
                 Circuits using Discrete Simulation",
  booktitle =    "18th European Conference on Genetic Programming",
  year =         "2015",
  editor =       "Penousal Machado and Malcolm I. Heywood and 
                 James McDermott and Mauro Castelli and 
                 Pablo Garcia-Sanchez and Paolo Burelli and Sebastian Risi and Kevin Sim",
  series =       "LNCS",
  volume =       "9025",
  publisher =    "Springer",
  pages =        "66--77",
  address =      "Copenhagen",
  month =        "8-10 " # apr,
  organisation = "EvoStar",
  keywords =     "genetic algorithms, genetic programming, Cartesian
                 genetic programming, EHW, Evolutionary design,
                 Transistor-level, Digital circuits",
  isbn13 =       "978-3-319-16500-4",
  DOI =          "doi:10.1007/978-3-319-16501-1_6",
  abstract =     "The objective of the paper is to introduce a new
                 approach to the evolutionary design of digital circuits
                 conducted directly at transistor level. In order to
                 improve the time consuming evaluation of candidate
                 solutions, a discrete event-driven simulator was
                 introduced. The proposed simulator operates on multiple
                 logic levels to achieve reasonable trade-off between
                 performance and precision. A suitable level of
                 abstraction reflecting the behaviour of real MOSFET
                 transistors is used to minimise the production of
                 incorrectly working circuits. The proposed approach is
                 evaluated in the evolution of basic logic circuits
                 having more than 20 transistors. The goal of the
                 evolutionary algorithm is to design a circuit having
                 the minimal number of transistors and exhibiting the
                 minimal delay. In addition to that, various parameter
                 settings are investigated to increase the success rate
                 of the evolutionary design.",
  notes =        "Part of \cite{Machado:2015:GP} EuroGP'2015 held in
                 conjunction with EvoCOP2015, EvoMusArt2015 and
                 EvoApplications2015",
}

Genetic Programming entries for Vojtech Mrazek Zdenek Vasicek

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