Role of circuit representation in evolutionary design of energy-efficient approximate circuits

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@Article{Mrazek:2018:IETcdt,
  author =       "Vojtech Mrazek and Zdenek Vasicek and Radek Hrbacek",
  title =        "Role of circuit representation in evolutionary design
                 of energy-efficient approximate circuits",
  journal =      "IET Computers \& Digital Techniques",
  year =         "2018",
  volume =       "12",
  number =       "4",
  pages =        "139--149",
  month =        jul,
  keywords =     "genetic algorithms, genetic programming",
  ISSN =         "1751-8601",
  DOI =          "doi:10.1049/iet-cdt.2017.0188",
  URL =          "http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2017.0188",
  abstract =     "Circuit approximation has been introduced in recent
                 years as a viable method for constructing
                 energy-efficient electronic systems. An open problem is
                 how to effectively obtain approximate circuits showing
                 good compromises between key circuit parameters -- the
                 error, power consumption, area and delay. The use of
                 evolutionary algorithms in the task of circuit
                 approximation has led to promising results.
                 Unfortunately, only relatively small circuit instances
                 have been tackled because of the scalability problems
                 of the evolutionary design method. This study
                 demonstrates how to push the limits of the evolutionary
                 design by choosing a more suitable representation on
                 the one hand and a more efficient fitness function on
                 the other hand. In particular, the authors show that
                 employing full adders as building blocks leads to more
                 efficient approximate circuits. The authors focused on
                 the approximation of key arithmetic circuits such as
                 adders and multipliers. While the evolutionary design
                 of adders represents a rather easy benchmark problem,
                 the design of multipliers is known to be one of the
                 hardest problems. The authors evolved a comprehensive
                 library of energy-efficient 12-bit multipliers with a
                 guaranteed worst-case error. The library consists of 65
                 Pareto dominant solutions considering power, delay,
                 area and error as design objectives.",
}

Genetic Programming entries for Vojtech Mrazek Zdenek Vasicek Radek Hrbacek

Citations