Genetic programming approach for SoC/IP floorplanning applications

Created by W.Langdon from gp-bibliography.bib Revision:1.4420

  author =       "Phuong Hong Phan and Thanh Duc Tong",
  title =        "Genetic programming approach for SoC/IP floorplanning
  booktitle =    "International Conference on Advanced Technologies for
                 Communications (ATC 2010)",
  year =         "2010",
  month =        "20-22 " # oct,
  pages =        "291--296",
  address =      "siagon",
  abstract =     "This paper presents a new solution for a System on
                 Chip/Intellectual Property (SoC/IP) module
                 floorplanning problem using genetic programming (GP)
                 technique. An example is demonstrated including 42
                 rectangular modules optimally arranged on a floor plan
                 based on the criterion of minimised Dead Space Ratio
                 (DSR). It is shown that the proposed approach saves
                 considerably the calculation time as the information of
                 each arrangement time is memorised and updated for the
                 next time without searching or comparing data.
                 Therefore, it can be used for a floorplanning problem
                 with a large number of modules.",
  keywords =     "genetic algorithms, genetic programming, IP
                 floorplanning applications, SoC, dead space ratio,
                 circuit layout, system-on-chip",
  DOI =          "doi:10.1109/ATC.2010.5672733",
  notes =        "Dept. of Telecommun. Eng., HCMC Univ. of Technol., Ho
                 Chi Minh City, Vietnam Also known as \cite{5672733}",

Genetic Programming entries for Phuong Hong Phan Thanh Duc Tong