Design and Simulation of Virtual Reconfigurable Circuit for a Fault Tolerant System

Created by W.Langdon from gp-bibliography.bib Revision:1.4340

  author =       "Atul K. Srivastava and Amav Gupta and 
                 Saurabh Chaturvedi and Vasu Rastogi",
  title =        "Design and Simulation of Virtual Reconfigurable
                 Circuit for a Fault Tolerant System",
  booktitle =    "Recent Advances and Innovations in Engineering (ICRAIE
  year =         "2014",
  month =        may,
  keywords =     "genetic algorithms, genetic programming, Cartesian
                 Genetic Programming, EHW, Fault detection, FPGA, PE,
                 Reconfiguration, VRC",
  DOI =          "doi:10.1109/ICRAIE.2014.6909277",
  size =         "4 pages",
  abstract =     "Evolvable Hardware (EHW) refers to hardware that can
                 change its architecture and behaviour dynamically and
                 autonomously by interacting with its environment. This
                 paper presents a new approach to on-line fault
                 tolerance via reconfiguration of the Programmable
                 Elements (PE) mapped onto field programmable gate
                 arrays (FPGAs). A grid of PE is programmed on the FPGA
                 structure. A complete hardware implementation of an
                 evolvable combinational unit for FPGAs is then
                 performed. The proposed combinational PE grid on FPGA
                 is used as virtual reconfigurable circuit (VRC).
                 Cartesian Genetic Programming (CGP), genetic operators
                 are described in Verilog - HDL and used to reprogram
                 the VRC. In all the cases the unit is able to evolve
                 (i.e. to design) the required function automatically
                 and autonomously, with a maximum delay of 22.82ns (when
                 logic level is 16) which is 40percent lower than
                 previous attempts. The design parameters of the
                 proposed architecture are also discussed. The fault
                 detection, based on self-checking technique can detect
                 the faults of PEs and routing interconnections in the
                 FPGAs concurrently with the normal system work. After
                 locating the faulty PE, the VRC will be reconfigured
                 using reserved PEs.",
  notes =        "Dept. of Electron. & Commun. Eng, Jaypee Inst. of Inf.
                 Technol., Noida, India Also known as \cite{6909277}",

Genetic Programming entries for Atul K Srivastava Amav Gupta Saurabh Chaturvedi Vasu Rastogi