Circuit segmentation using GP in FPGA's technology mapping

Created by W.Langdon from gp-bibliography.bib Revision:1.4504

  author =       "Atul K. Srivastava and Himanshu Shishodia and 
                 Himanshu Jaypee",
  booktitle =    "2016 3rd International Conference on Computing for
                 Sustainable Global Development (INDIACom)",
  title =        "Circuit segmentation using {GP} in {FPGA's} technology
  year =         "2016",
  pages =        "1947--1951",
  month =        mar,
  keywords =     "genetic algorithms, genetic programming, EHW,
                 technology mapping, circuit segmentation, FPGA",
  URL =          "",
  size =         "5 pages",
  abstract =     "In this paper an algorithm for efficient technology
                 mapping in FPGAs using circuit segmentation is proposed
                 and implemented. In this paper area minimization of the
                 circuit along with the optimal use of Table Look Ups
                 (TLU) in the existing library, with minimum redundancy
                 is discussed. The algorithm has been tested on ISCAS'85
                 bench mark and other circuits. The results show
                 considerable improvement in the technology mapping with
                 respect to area optimisation of the circuit minimised
  notes =        "Also known as \cite{7724605}",

Genetic Programming entries for Atul K Srivastava Himanshu Shishodia Himanshu Jaypee