Acceleration of transistor-level evolution using Xilinx Zynq Platform

Created by W.Langdon from gp-bibliography.bib Revision:1.4496

@InProceedings{Vasicek:2014:ICES,
  author =       "Vojtech Mrazek and Zdenek Vasicek",
  title =        "Acceleration of transistor-level evolution using
                 Xilinx Zynq Platform",
  booktitle =    "2014 IEEE International Conference on Evolvable
                 Systems",
  year =         "2014",
  pages =        "9--16",
  address =      "Orlando, FL, USA",
  month =        "9-12 " # dec,
  publisher =    "IEEE",
  keywords =     "genetic algorithms, genetic programming",
  isbn13 =       "978-1-4799-4479-8",
  DOI =          "doi:10.1109/ICES.2014.7008716",
  size =         "8 pages",
  abstract =     "the aim of this paper is to introduce a new
                 accelerator developed to address the problem of
                 evolutionary synthesis of digital circuits at
                 transistor level. The proposed accelerator, based on
                 recently introduced Xilinx Zynq platform, consists of a
                 discrete simulator implemented in programmable logic
                 and an evolutionary algorithm running on a tightly
                 coupled embedded ARM processor. The discrete simulator
                 was introduced in order to achieve a good trade-off
                 between the precision and performance of the simulation
                 of transistor-level circuits. The simulator is
                 implemented using the concept of virtual reconfigurable
                 circuit and operates on multiple logic levels which
                 enables to evaluate the behavior of candidate
                 transistor-level circuits at a reasonable level of
                 detail. In this work, the concept of virtual
                 reconfigurable circuit was extended to enable
                 bidirectional data flow which represents the basic
                 feature of transistor level circuits. According to the
                 experimental evaluation, the proposed architecture
                 speeds up the evolution in one order of magnitude
                 compared to an optimized software implementation. The
                 developed accelerator is used in the evolution of basic
                 logic circuits having up to 5 inputs. It is shown that
                 solutions competitive to the circuits obtained by
                 conventional design methods can be discovered.",
  notes =        "Also known as \cie{t7008716}",
}

Genetic Programming entries for Vojtech Mrazek Zdenek Vasicek

Citations