Search-Based Synthesis of Approximate Circuits Implemented into FPGAs

Created by W.Langdon from gp-bibliography.bib Revision:1.4549

  author =       "Zdenek Vasicek and Lukas Sekanina",
  title =        "Search-Based Synthesis of Approximate Circuits
                 Implemented into FPGAs",
  booktitle =    "26th International Conference on Field-Programmable
                 Logic and Applications",
  year =         "2016",
  editor =       "Jason Anderson and Philip Brisk",
  address =      "Lausanne, Switzerland",
  month =        "29 " # aug # "-2 " # sep,
  organisation = "EPFL",
  publisher =    "IEEE",
  keywords =     "genetic algorithms, genetic programming, cartesian
                 genetic programming",
  URL =          "",
  DOI =          "doi:10.1109/FPL.2016.7577305",
  size =         "4 pages",
  abstract =     "Approximate computing is capable of exploiting the
                 error resilience of various applications with the aim
                 of improving their parameters such as performance,
                 energy consumption and area on a chip. In this paper, a
                 new systematic approach for the approximation and
                 optimization of circuits intended for LUT-based field
                 programmable gate arrays (FPGAs) is proposed. In order
                 to deliver a good trade-off between the quality of
                 processing and implementation cost, the method employs
                 a genetic programming-based optimization engine. The
                 circuits are internally represented and optimized at
                 the gate level. The resulting LUT-based netlists are
                 obtained using a commercial FPGA tool. In the
                 experimental part, four commonly available commercial
                 FPGA design tools (Xilinx ISE, Xilinx Vivado,
                 Precision, and Quartus) and state-of-the-art academia
                 circuit synthesis and optimization tool ABC are
                 compared. The quality of approximated circuits is
                 evaluated using relaxed equivalence checking by means
                 of Binary decision diagrams. An important conclusion is
                 that the improvements (i.e. area reductions) at the
                 gate level are preserved by the FPGA design tools and
                 thus the number of LUTs is also adequately reduced. It
                 was shown that the current state-of-the-art synthesis
                 tools provide (for some instances) the results that are
                 far from an optimum. For example, a 40percent reduction
                 (68 LUTs) was achieved for clmb benchmark circuit (Bus
                 Interface) without introducing any error. Additional
                 43percent reduction can be obtained by introducing only
                 a 0.1percent error.",
  notes =        "slides

                 Also known as \cite{7577305}",

Genetic Programming entries for Zdenek Vasicek Lukas Sekanina