Cartesian genetic algorithm for Boolean synthesis with power consumption restriction

Created by W.Langdon from gp-bibliography.bib Revision:1.3872

  author =       "J. Vitola and C. Pedraza and J. I. Martinez and 
                 J. Sepulveda",
  booktitle =    "5th IEEE Colombian Workshop on Circuits and Systems
                 (CWCAS 2014)",
  title =        "Cartesian genetic algorithm for Boolean synthesis with
                 power consumption restriction",
  year =         "2014",
  month =        oct,
  abstract =     "The use of evolutionary algorithms in the Boolean
                 synthesis is an interesting technique to generate
                 hardware structures with multiple restrictions.
                 However, one characteristic of these algorithms is
                 their high computational load. This paper presents the
                 implementation of a parallel cartesian genetic
                 programming (CGP) for Boolean synthesis on a FPGA-CPU
                 based platform. Power consumption and critical path
                 restrictions were included into the algorithm in order
                 to generate structures to solve any problem. As results
                 a 2-bit comparator is presented, as well as response
                 time and data transitions probability.",
  keywords =     "genetic algorithms, genetic programming, cartesian
                 genetic programming",
  DOI =          "doi:10.1109/CWCAS.2014.6994608",
  notes =        "Also known as \cite{6994608}",

Genetic Programming entries for Jaime Vitola Cesar Pedraza Bonilla J I Martinez Martha Johanna Sepulveda Florez