Created by W.Langdon from gp-bibliography.bib Revision:1.3872

@InProceedings{alganova:2000:efemvlf, author = "Tatiana Kalganova", title = "An Extrinsic Function-Level Evolvable Hardware Approach", booktitle = "Genetic Programming, Proceedings of EuroGP'2000", year = "2000", editor = "Riccardo Poli and Wolfgang Banzhaf and William B. Langdon and Julian F. Miller and Peter Nordin and Terence C. Fogarty", volume = "1802", series = "LNCS", pages = "60--75", address = "Edinburgh", publisher_address = "Berlin", month = "15-16 " # apr, organisation = "EvoNet", publisher = "Springer-Verlag", keywords = "genetic algorithms, genetic programming", ISBN = "3-540-67339-3", URL = "http://citeseer.ist.psu.edu/cache/papers/cs/12975/http:zSzzSzwww.dcs.napier.ac.ukzSz~tatianazSzpaperszSzkalganova_EuroGP2000.pdf/kalganova00extrinsic.pdf", URL = "http://citeseer.ist.psu.edu/kalganova00extrinsic.html", URL = "http://www.springerlink.com/openurl.asp?genre=article&issn=0302-9743&volume=1802&spage=60", DOI = "doi:10.1007/978-3-540-46239-2_5", abstract = "The function level evolvable hardware approach to synthesize the combinational multi-valued and binary logic functions is proposed in first time. The new representation of logic gate in extrinsic EHW allows us to describe behaviour of any multi-input multi-output logic function. The circuit is represented in the form of connections and functionalities of a rectangular array of building blocks. Each building block can implement primitive logic function or any multi-input multi-output logic function defined in advance. The method has been tested on evolving logic circuits using half adder, full adder and multiplier. The effectiveness of this approach is investigated for multi-valued and binary arithmetical functions. For these functions either method appears to be much more efficient than similar approach with two-input one-output cell representation.", notes = "EuroGP'2000, part of \cite{poli:2000:GP}", }

Genetic Programming entries for Tatiana Kalganova