Designing Optimal Combinational Digital Circuits Using a Multiple Logic Unit Processor

Created by W.Langdon from gp-bibliography.bib Revision:1.3973

@InProceedings{cheang:2004:eurogp,
  author =       "Sin Man Cheang and Kin Hong Lee and Kwong Sak Leung",
  title =        "Designing Optimal Combinational Digital Circuits Using
                 a Multiple Logic Unit Processor",
  booktitle =    "Genetic Programming 7th European Conference, EuroGP
                 2004, Proceedings",
  year =         "2004",
  editor =       "Maarten Keijzer and Una-May O'Reilly and 
                 Simon M. Lucas and Ernesto Costa and Terence Soule",
  volume =       "3003",
  series =       "LNCS",
  pages =        "23--34",
  address =      "Coimbra, Portugal",
  publisher_address = "Berlin",
  month =        "5-7 " # apr,
  organisation = "EvoNet",
  publisher =    "Springer-Verlag",
  keywords =     "genetic algorithms, genetic programming",
  ISBN =         "3-540-21346-5",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0302-9743&volume=3003&spage=23",
  size =         "12 pages",
  DOI =          "doi:10.1007/978-3-540-24650-3_3",
  abstract =     "Genetic Parallel Programming (GPP) is a novel Genetic
                 Programming paradigm. The GPP Accelerating Phenomenon,
                 i.e. parallel programs are easier to be evolved than
                 sequential programs, opens up a new approach to evolve
                 solution programs in parallel forms. Based on the GPP
                 paradigm, we developed a combinational digital circuit
                 learning system, the GPP+MLP system. An optimal
                 Multiple Logic Unit Processor (MLP) is designed to
                 evaluate genetic parallel programs. To show the
                 effectiveness of the proposed GPP+MLP system, four
                 multi-output Binary arithmetic circuits are used.
                 Experimental results show that both the gate counts and
                 the propagation gate delays of the evolved circuits are
                 less than conventional designs. For example, in a 3-bit
                 multiplier experiment, we obtained a combinational
                 digital circuit with 26 two-input logic gates in 6 gate
                 levels. It uses 4 gates less than a conventional
                 design.",
  notes =        "Part of \cite{keijzer:2004:GP} EuroGP'2004 held in
                 conjunction with EvoCOP2004 and EvoWorkshops2004",
}

Genetic Programming entries for Ivan Sin Man Cheang Kin-Hong Lee Kwong-Sak Leung

Citations