Multi-logic-Unit Processor: A Combinational Logic Circuit Evaluation Engine for Genetic Parallel Programming

Created by W.Langdon from gp-bibliography.bib Revision:1.3872

@InProceedings{eurogp:LauLLLC05,
  author =       "Wai Shing Lau and Gang Li and Kin-Hong Lee and 
                 Kwong-Sak Leung and Sin Man Cheang",
  editor =       "Maarten Keijzer and Andrea Tettamanzi and 
                 Pierre Collet and Jano I. {van Hemert} and Marco Tomassini",
  title =        "Multi-logic-Unit Processor: A Combinational Logic
                 Circuit Evaluation Engine for Genetic Parallel
                 Programming",
  booktitle =    "Proceedings of the 8th European Conference on Genetic
                 Programming",
  publisher =    "Springer",
  series =       "Lecture Notes in Computer Science",
  volume =       "3447",
  year =         "2005",
  address =      "Lausanne, Switzerland",
  month =        "30 " # mar # " - 1 " # apr,
  organisation = "EvoNet",
  keywords =     "genetic algorithms, genetic programming",
  ISBN =         "3-540-25436-6",
  pages =        "167--177",
  DOI =          "doi:10.1007/b107383",
  bibsource =    "DBLP, http://dblp.uni-trier.de",
  abstract =     "Genetic Parallel Programming (GPP) is a novel Genetic
                 Programming paradigm. GPP Logic Circuit Synthesiser
                 (GPPLCS), is a combinational logic circuit learning
                 system based on GPP. The GPPLCS comprises a
                 Multi-Logic-Unit Processor (MLP) which is a hardware
                 processor built on a Field Programmable Gate Array
                 (FPGA). The MLP is designed to speed up the evaluation
                 of genetic parallel programs that represent
                 combinational logic circuits. Four combinational logic
                 circuit problems are presented to show the performance
                 of the hardware-assisted GPPLCS. Experimental results
                 show that the hardware MLP speeds up evolutions over 10
                 times. For difficult problems such as the 6-bit
                 priority selector and the 6-bit comparator, the speedup
                 ratio can be up to 22.",
  notes =        "Part of \cite{keijzer:2005:GP} EuroGP'2005 held in
                 conjunction with EvoCOP2005 and EvoWorkshops2005",
}

Genetic Programming entries for Wai Shing Lau Gang Li Kin-Hong Lee Kwong-Sak Leung Ivan Sin Man Cheang

Citations