Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System

Created by W.Langdon from gp-bibliography.bib Revision:1.4549

  title =        "Lookup Table Partial Reconfiguration for an Evolvable
                 Hardware Classifier System",
  author =       "Kyrre Glette and Paul Kaufmann",
  pages =        "1706--1713",
  booktitle =    "Proceedings of the 2014 IEEE Congress on Evolutionary
  year =         "2014",
  month =        "6-11 " # jul,
  editor =       "Carlos A. {Coello Coello}",
  address =      "Beijing, China",
  ISBN =         "0-7803-8515-2",
  keywords =     "genetic algorithms, genetic programming, EHW, Hardware
                 Aspects of Bio-Inspired Architectures and Systems
  DOI =          "doi:10.1109/CEC.2014.6900503",
  size =         "8 pages",
  abstract =     "The evolvable hardware (EHW) paradigm relies on
                 continuous run-time reconfiguration of hardware. When
                 applied on modern FPGAs, the technically challenging
                 reconfiguration process becomes an issue and can be
                 approached at multiple levels. In related work, virtual
                 reconfigurable circuits (VRC), partial reconfiguration,
                 and lookup table (LUT) reconfiguration approaches have
                 been investigated. In this paper, we show how
                 fine-grained partial reconfiguration of 6-input LUTs of
                 modern Xilinx FPGAs can lead to significantly more
                 efficient resource use in an EHW application. Neither
                 manual placement nor any proprietary bitstream
                 manipulation is required in the simplest form of the
                 employed method. We specify the goal architecture in
                 VHDL and read out the locations of the automatically
                 placed LUTs for use in an on line reconfiguration
                 setting. This allows for an easy and flexible
                 architecture specification, as well as possible
                 implementation improvements over a hand-placed design.
                 For demonstration, we rely on a hardware signal
                 classifier application. Our results show that the
                 proposed approach can fit a classification circuit 4
                 times larger than an equivalent VRC-based approach, and
                 6 times larger than a shift register-based approach, in
                 a Xilinx Virtex-5 device. To verify the reconfiguration
                 process, a MicroBlaze-based embedded system is
                 implemented, and reconfiguration is carried out via the
                 Xilinx Internal Configuration Access Port (ICAP) and
                 driver software.",
  notes =        "Also known as \cite{Glette:2014:CEC}",

Genetic Programming entries for Kyrre Harald Glette Paul Kaufmann