Towards Self-Adaptive Caches: a Run-Time Reconfigurable Multi-Core Infrastructure

Created by W.Langdon from gp-bibliography.bib Revision:1.4504

  author =       "Nam Ho and Paul Kaufmann and Marco Platzner",
  title =        "Towards Self-Adaptive Caches: a Run-Time
                 Reconfigurable Multi-Core Infrastructure",
  booktitle =    "International Conference on Evolvable Systems, ICES
  year =         "2014",
  pages =        "31--37",
  month =        "9-12 " # dec,
  publisher =    "IEEE",
  keywords =     "genetic algorithms, genetic programming, Cartesian
                 Genetic Programming, EHW",
  DOI =          "doi:10.1109/ICES.2014.7008719",
  size =         "7 page",
  abstract =     "This paper presents the first steps towards the
                 implementation of an evolvable and self-adaptable
                 processor cache. The implemented system consists of a
                 run-time reconfigurable memory-to-cache address mapping
                 engine embedded into the split level one cache of a
                 Leon3 SPARC processor as well as of an measurement
                 infrastructure able to profile microarchitectural and
                 custom logic events based on the standard Linux
                 performance measurement interface perf_event. The
                 implementation shows, how reconfiguration of the very
                 basic processor properties, and fine granular profiling
                 of custom logic and integer unit events can be realised
                 and meaningfully used to create an adaptable multi-core
                 embedded system.",
  notes =        "EvoCache Xilinx FPGA. Also known as \cite{7008719}",

Genetic Programming entries for Nam Ho Paul Kaufmann Marco Platzner